Welcome to the Real-Time and Embedded Systems Lab at Saarland University!
We conduct research on design and analysis problems at the boundary between hardware and software.
Our recent work has focused on the following topics:
- Design of Timing-Predictable Microarchitectures
- Timing Analysis for Software Systems deployed on Multi-core Architectures
- Security in the Presence of Microarchitectural Side Channels
- Automatic Derivation of Detailed Performance Models of Modern Hardware Platforms
- April 2019: Sebastian Hahn successfully defended his doctoral dissertation. Congratulations to Dr. Hahn!
- March 2019: Our article on the incomparability of cache algorithms in terms of timing leakage has appeared in Logical Methods in Computer Science (LMCS).
- December 2018: Our paper "Fast and Exact Analysis for LRU Caches" has been accepted to POPL 2019.
- November 2018: Our paper "uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures" has been accepted to ASPLOS 2019.
- November/December 2018: Our paper "Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core" to appear at RTSS this year, has been named an Outstanding paper and Best Student paper.
- October 2018: uops.info is online! The site contains more than 200,000 pages with detailed latency, throughput, and port usage data for most x86 instructions on all generations of Intel's Core architecture (i.e., from Nehalem to Coffee Lake). While such data is important for understanding, predicting, and optimizing the performance of software running on these microarchitectures, most of it is not documented in Intel's official processor manuals.
- October 2018: Our article on the semantic foundations of cache persistence analysis has appeared in the LITES journal. It shows how all prior analyses can be proved correct in a single unified framework.
- August 2018: We are grateful to Intel for their generous gift to support our research on "Information Flow Tracking across the Hardware-Software Boundary".
- July 2018: Our article on the multi-core timing analysis has appeared in the Real-Time Systems journal.
- July 2017: Our paper "Memory Bank Partitioning for Fixed-Priority Tasks in a Multi-Core System" has been accepted to RTSS 2017.
- May 2017: Our paper "Write-back Caches in WCET Analysis", to appear at ECRTS this year, has been named an Outstanding paper.
- April 2017: Our paper "Ascertaining Uncertainty for Efficient Exact Cache Analysis" has been accepted to CAV 2017.
- February 2017: Our POST paper has been nominated for the Best ETAPS Paper award!
- October 2016: Our paper on "Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling" has been named an Outstanding Paper at RTNS 2016!
- June 2016: Our survey article on cache analysis has appeared in the Leibniz Transactions on Embedded Systems.
- June 2016: Jan is a panelist at DAC on Predictable System Timing – Probab(ilistical)ly?
- March 2016: Our DFG project proposal "PEP: Precise and Efficient Prediction of Good Worst-case Performance for Contemporary and Future Architectures" has been granted!
- February 2016: Our paper "MIRROR: Symmetric Timing Analysis for Real-Time Tasks on Multicore Platforms with Shared Resources" with coauthors Wen-Hung Huang and Jian-Jia Chen has been accepted to DAC 2016.
- November 2015: Our paper on A Generic and Compositional Framework for Multicore Response Time Analysis appears at RTNS 2015 and has been named an Outstanding Paper!
- October 2015: Jan is giving an invited talk about cache-related preemption delay at TELECOM ParisTech.
- July 2015: Our paper on the smoothness of paging algorithms has been accepted to WAOA 2015.
- June 2015: Our article on quantifying cache side channels has appeared in the ACM Transactions on Information and System Security.
- June 2015: Our paper on the minimization of incompletely-specified Mealy machines has been accepted to ICCAD 2015.
- October 2014: Our paper on A Compiler Optimization to Increase the Efficiency of WCET Analysis appears at RTNS 2014 and has been named an Outstanding Paper!
- June 2014: Randomized Caches Considered Harmful!
- January 2014: Our papers on Architecture-Parametric Timing Analysis and Selfish-LRU have been accepted to RTAS 2014.
- January 2014: Our paper on Basic Problems in Multi-View Modeling has been accepted to TACAS 2014.
- The survey about the impact of resource sharing on performance and performance prediction that we wrote as part of a doctoral privatissimum will appear in CONCUR 2013.
- June 2013: Our paper on the static analysis of cache side channels has been accepted to USENIX Security 2013.
- April 2013: Jan gave an Intel Tech Talk at Intel Braunschweig on challenges for WCET analysis of contemporary microarchitectures.
- August 2012: Jan Reineke has received an Intel Early Career Faculty Award!