Sebastian Hahn

Real-Time and Embedded Systems Lab
Universität des Saarlandes
Phone: +49 681 302 5571
Building: E 1 3 Room: 402
Coordinates: N 49.257833° E 7.045144°

Short CV

I joined the group of Jan Reineke in 2013.
Prior to that, I worked on relational cache analysis in the group of Reinhard Wilhelm advised by Daniel Grund. I completed my B.Sc. on relational cache analysis in late 2011. Since 2012, I am a member of the Graduate School of Computer Science at Saarland University.
I received my M.Sc. on a formal definition of timing compositionality in early 2015.
Until the end of 2015, I was part of the DFG SFB/TR 14 Automatic Verification and Analysis of Complex Systems working on timing compositionality.
From 2017 on, I work on timing-predictable processor designs and corresponding timing analyses within the DFG project "PEP: Precise and Efficient Prediction of Good Worst-case Performance for Contemporary and Future Architectures".

Research Interests


Winter 2016/2017, Winter 2018/2019

Summer 2015, Winter 2017/2018

Summer 2014, Summer 2016, Summer 2017

Winter 2012/2013

Summer 2012

Thesis Advisor


Journal PapersConference and Workshop PapersMasters ThesisBachelors Thesis

Journal Papers

  1. Towards compositionality in execution time analysis: definition and challenges
    S. Hahn, J. Reineke, and R. Wilhelm
    SIGBED Review, 12(1), 2015
    [doi] [bib]

Conference and Workshop Papers

  1. Cache Persistence Analysis: Finally Exact
    G. Stock, S. Hahn, and J. Reineke
    RTSS, December 2019
  2. Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
    S. Hahn and J. Reineke
    RTSS, December 2018
    [pdf] [pdf slides] [bib]
  3. Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis
    D. Shah, S. Hahn, and J. Reineke
    WCET, July 2018
  4. Write-Back Caches in WCET Analysis
    T. Blaß , S. Hahn, and J. Reineke
    ECRTS, 2017
    [doi] [pdf] [pdf slides] [bib]
  5. Enabling Compositionality for Multicore Timing Analysis
    S. Hahn, M. Jacobs, and J. Reineke
    RTNS, October 2016
    [doi] [pdf] [bib]
  6. Toward Compact Abstractions for Processor Pipelines
    S. Hahn, J. Reineke, and R. Wilhelm
    Correct System Design - Symposium in Honor of Ernst-Rüdiger Olderog on the Occasion of His 60th Birthday, Oldenburg, Germany, September 8-9, 2015. Proceedings, 2015
    [doi] [pdf] [bib]
  7. Selfish-LRU: Preemption-aware caching for predictability and performance
    J. Reineke, S. Altmeyer, D. Grund, S. Hahn, and C. Maiza
    RTAS, April 2014
    [doi] [pdf] [pdf slides] [bib]
  8. Impact of Resource Sharing on Performance and Performance Prediciton: A Survey
    A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn, F. Haupenthal, M. Jacobs, A. Moin, J. Reineke, B. Schommer, and R. Wilhelm
    CONCUR, August 2013
    [doi] [pdf] [bib]
  9. Towards Compositionality in Execution Time Analysis -- Definition and Challenges
    S. Hahn, J. Reineke, and R. Wilhelm
    CRTS, December 2013
    [pdf] [bib]

Masters Thesis

  1. Defining Compositionalty in Execution Time Analysis
    S. Hahn
    Universität des Saarlandes, Germany, 2014
    [pdf] [bib]

Bachelors Thesis

  1. Towards Relational Cache Analysis
    S. Hahn
    Saarland University, 2011

A list of publications can also be found on DBLP.