In 2012, he was selected
as an Intel Early Career Faculty Honor Program awardee. He was the PC chair of EMSOFT 2014, the International Conference on Embedded Software, a Topic co-chair at DATE 2016 and the PC chair of WCET 2017, the International Workshop on Worst-Case Execution Time Analysis.
His papers have been awarded 9 outstanding paper awards and two best-paper nominations, most recently at DATE (2024), CCS (2023), RTSS (2023, 2019, 2018), Oakland (2021), and ECRTS (2017).
In 2021, he has been awarded an ERC Advanced Grant.
- Fast and Exact Analysis for LRU Caches
V. Touzeau, C. Maïza, D. Monniaux, and J. Reineke
Proc. ACM Program. Lang., 3(POPL), January 2019
[doi] [bib]@article{Touzeau19,
title = {Fast and Exact Analysis for LRU Caches},
acmid = {3290367},
address = {New York, NY, USA},
articleno = {54},
author = {Touzeau, Valentin and Ma\"{\i }za, Claire and Monniaux, David and Reineke, Jan},
doi = {10.1145/3290367},
issn = {2475-1421},
issue_date = {January 2019},
journal = {Proc. ACM Program. Lang.},
keyword = {Abstract Interpretation, Cache Analysis, LRU},
month = {Jan},
number = {POPL},
numpages = {29},
pages = {54:1--54:29},
publisher = {ACM},
url = {http://doi.acm.org/10.1145/3290367},
volume = {3},
year = {2019}
}
- An extensible framework for multicore response time analysis
R. Davis, S. Altmeyer, L. Indrusiak, C. Maiza, V. Nelis, and J. Reineke
Real-Time Systems, 54(3), July 2018
[doi] [bib]@article{Davis18a,
title = {An extensible framework for multicore response time analysis},
abstract = {In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on context-independent WCET values. Instead, the analysis formulates response times directly from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.},
author = {Davis, Robert I. and Altmeyer, Sebastian and Indrusiak, Leandro S. and Maiza, Claire and Nelis, Vincent and Reineke, Jan},
day = {01},
doi = {10.1007/s11241-017-9285-4},
issn = {1573-1383},
journal = {Real-Time Systems},
month = {Jul},
number = {3},
pages = {607--661},
url = {https://doi.org/10.1007/s11241-017-9285-4},
volume = {54},
year = {2018}
}
- The Semantic Foundations and a Landscape of Cache-Persistence Analyses
J. Reineke
LITES, 5(1), 2018
[doi] [bib]@article{Reineke18a,
title = {The Semantic Foundations and a Landscape of Cache-Persistence Analyses},
author = {Reineke, Jan},
doi = {10.4230/LITES-v005-i001-a003},
journal = {{LITES}},
number = {1},
pages = {03:1--03:52},
url = {https://doi.org/10.4230/LITES-v005-i001-a003},
volume = {5},
year = {2018}
}
- CacheAudit: A Tool for the Static Analysis of Cache Side Channels
G. Doychev, B. Köpf, L. Mauborgne, and J. Reineke
ACM Trans. Inf. Syst. Secur., 18(1), June 2015
[doi] [pdf] [bib]@article{Doychev15,
title = {{CacheAudit}: A Tool for the Static Analysis of Cache Side Channels},
acmid = {2756550},
address = {New York, NY, USA},
articleno = {4},
author = {Doychev, Goran and K{\"o}pf, Boris and Mauborgne, Laurent and Reineke, Jan},
doi = {10.1145/2756550},
issn = {1094-9224},
issue_date = {June 2015},
journal = {ACM Trans. Inf. Syst. Secur.},
keyword = {Side-channel attacks, caches},
month = {Jun},
number = {1},
numpages = {32},
pages = {4:1--4:32},
publisher = {ACM},
url = {http://doi.acm.org/10.1145/2756550},
volume = {18},
year = {2015}
}
- Towards compositionality in execution time analysis: definition and challenges
S. Hahn, J. Reineke, and R. Wilhelm
SIGBED Review, 12(1), 2015
[doi] [bib]@article{Hahn15,
title = {Towards compositionality in execution time analysis: definition and challenges},
author = {Hahn, Sebastian and Reineke, Jan and Wilhelm, Reinhard},
bibsource = {dblp computer science bibliography, http://dblp.org},
biburl = {http://dblp.uni-trier.de/rec/bib/journals/sigbed/0001RW15},
doi = {10.1145/2752801.2752805},
journal = {{SIGBED} Review},
number = {1},
pages = {28--36},
timestamp = {Sat, 25 Apr 2015 19:50:05 +0200},
url = {http://doi.acm.org/10.1145/2752801.2752805},
volume = {12},
year = {2015}
}
- Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis (Outstanding Paper Award )
V. Touzeau and J. Reineke
RTSS, 2023
[bib]@inproceedings{Touzeau23,
title = {Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis},
author = {Touzeau, Valentin and Reineke, Jan},
booktitle = {2023 {IEEE} Real-Time Systems Symposium, {RTSS} 2023, Taipei, Taiwan, December 5-8, 2023},
year = {2023}
}
- Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts (Distinguished Paper Award )
Z. Wang, G. Mohr, K. Gleissenthall, J. Reineke, and M. Guarnieri
CCS, 2023
[bib]@inproceedings{wang2023specification,
title = {Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts},
author = {Wang, Zilong and Mohr, Gideon and Gleissenthall, Klaus von and Reineke, Jan and Guarnieri, Marco},
booktitle = {Proceedings of the 30th ACM Conference on Computer and Communications Security},
publisher = {ACM},
series = {CCS 2023},
year = {2023}
}
- uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
A. Abel and J. Reineke
ICS, 2022
[bib]@inproceedings{Abel22,
title = {{uiCA}: Accurate Throughput Prediction of Basic Blocks on Recent {Intel} Microarchitectures},
author = {Abel, Andreas and Reineke, Jan},
booktitle = {{ICS} '22: 2022 International Conference on Supercomputing, Virtual Event, USA, June 27-30, 2022},
series = {ICS '22},
editor = {Rauchwerger, Lawrence and Cameron, Kirk and Nikolopoulos, Dimitrios S. and Pnevmatikatos, Dionisios},
pages = {1--12},
publisher = {{ACM}},
month = {June},
year = {2022},
url = {https://dl.acm.org/doi/pdf/10.1145/3524059.3532396}
}
- Warping Cache Simulation of Polyhedral Programs
C. Morelli and J. Reineke
PLDI, June 2022
[doi] [bib]@inproceedings{Morelli22,
title = {Warping Cache Simulation of Polyhedral Programs},
address = {New York, NY, USA},
author = {Morelli, Canberk and Reineke, Jan},
booktitle = {PLDI},
doi = {10.1145/3519939.3523714},
isbn = {978-1-4503-9265-5/22/06},
location = {San Diego, CA, USA},
numpages = {16},
publisher = {ACM},
series = {PLDI '22},
url = {http://doi.acm.org/10.1145/3519939.3523714},
month = {Jun},
year = {2022},
}
- Hardware-Software Contracts for Secure Speculation (Best Paper Award )
M. Guarnieri, B. Köpf, J. Reineke, and P. Vila
S&P (Oakland), May 2021
[bib]@inproceedings{Guarnieri21,
title = {Hardware-Software Contracts for Secure Speculation},
author = {Guarnieri, Marco and K{{\"o}}pf, Boris and Reineke, Jan and Vila, Pepe},
booktitle = {2021 {IEEE} Symposium on Security and Privacy, {SP} 2021, Proceedings, San Francisco, California, {USA}},
month = {May},
url = {https://arxiv.org/abs/2006.03841},
year = {2021}
}
- SPECTECTOR: Principled Detection of Speculative Information Flows
M. Guarnieri, B. Köpf, J. Morales, J. Reineke, and A. Sánchez
S&P (Oakland), May 2020
[pdf] [bib]@inproceedings{Guarnieri20,
title = {{SPECTECTOR:} Principled Detection of Speculative Information Flows},
author = {Guarnieri, Marco and K{{\"o}}pf, Boris and Morales, Jos{{\'e}} F. and Reineke, Jan and S{{\'a}}nchez, Andr{{\'e}}s},
booktitle = {2020 {IEEE} Symposium on Security and Privacy, {SP} 2020, Proceedings, San Francisco, California, {USA}},
month = {May},
url = {https://spectector.github.io/papers/spectector.pdf},
year = {2020}
}
- uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
A. Abel and J. Reineke
ASPLOS, 2019
[doi] [bib]@inproceedings{Abel19a,
title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on {Intel} Microarchitectures},
acmid = {3304062},
address = {New York, NY, USA},
author = {Abel, Andreas and Reineke, Jan},
booktitle = {ASPLOS},
doi = {10.1145/3297858.3304062},
isbn = {978-1-4503-6240-5},
location = {Providence, RI, USA},
numpages = {14},
pages = {673--686},
publisher = {ACM},
series = {ASPLOS '19},
url = {http://doi.acm.org/10.1145/3297858.3304062},
year = {2019}
}
- Cache Persistence Analysis: Finally Exact (Best Paper Award )
G. Stock, S. Hahn, and J. Reineke
RTSS, December 2019
[bib]@inproceedings{Stock19,
title = {Cache Persistence Analysis: Finally Exact},
author = {Stock, Gregory and Hahn, Sebastian and Reineke, Jan},
booktitle = {RTSS},
month = {Dec},
year = {2019}
}
- Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core (Best Student Paper Award )
S. Hahn and J. Reineke
RTSS, December 2018
[pdf] [pdf slides] [bib]@inproceedings{Hahn18,
title = {Design and Analysis of {SIC}: A Provably Timing-Predictable Pipelined Processor Core},
author = {Hahn, Sebastian and Reineke, Jan},
booktitle = {RTSS},
month = {Dec},
year = {2018}
}
- Abstract PRET Machines
E. Lee, J. Reineke, and M. Zimmer
RTSS, 2017
[doi] [bib]@inproceedings{Lee17,
title = {Abstract {PRET} Machines},
author = {Lee, Edward A. and Reineke, Jan and Zimmer, Michael},
booktitle = {2017 {IEEE} Real-Time Systems Symposium, {RTSS} 2017, Paris, France, December 5-8, 2017},
doi = {10.1109/RTSS.2017.00041},
pages = {1--11},
url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2017.00041},
year = {2017}
}